! ###############################################################
! ###############################################################
! ###                                                         ###
! ###  IOMD system level block models                         ###
! ###                                                         ###
! ###  Created 18/8/92: David Flynn                           ###
! ###                                                         ###
! ###  BUSCTL Main Bus Controller                             ###
! ###                                                         ###
! ###############################################################
! ###############################################################
! ###  Revision History:                                      ###
! ###   02/9/92: DWF : Removed <Nreset> from BUSCTL           ###
! ###   03/9/92: AS  : Added refresh logic & arbiter          ###
! ###   07/9/92: DWF : BUSCTL spilt from IOMDSYS file         ###
! ###   09/9/92: DWF : <Nreset> added to BUSARB to clear DMAs ###
! ###   15/9/92: DF  : rclk mergege logic synchronised in RCLK###
! ###   16/9/92: DWF : 2nd processor interface added to IOMD  ###
! ###   16/9/92: DF  : armrq renamed busrq with 2nd proc added ##
! ###   23/9/92: DF  : iomclk retimed with RCLK delayed form  ###
! ###   24/9/92: DF  : iomclk1 retimed with RCLK (clean \edge)###
! ###   29/9/92: DF  : state machine o/ps pruned, snd0 dma fix###
! ###   3/11/92: AS  : Delayed dbe, to stop ARM & DMA clashing###
! ###  11/12/92: DF  : Removed IOGOING from BUSARB and {O/P}  ###
!      14/1/93   WO    moved mclk generation to rclkgen       ###
!      20/1/93   WO    inverted sense of busrq for speed      ###
!      25/1/93   WO    gated rclk into romgo,ramgo,proggo so  ###
!                      that early dmarq (uldmarq) can be used ###
! ###############################################################

FROM StdParts.Misc         IMPORT  $SDTFF, $NSLatch, $SMux, $Sink
FROM StdParts.Gates        IMPORT  $SGate1, $SGate2, $SGate3

FROM iomd.bussm            IMPORT  bussm
FROM iomd.busarbc          IMPORT  $BUSARB


! ###############################################################
! dummy tie offs:

BLOCK SNK({IN} s)
  sink = $Sink(z(s, s))
END {SNK}


! ###############################################################
! IOMD BUSCTL Bus Controller (main bus statemachine)
! ###############################################################

BLOCK BUSCTL(
! clock signals
  {IN}  rclk,
  {IN}  mclk,
! arm/2nd proc bus request
  {IN}  Nmreq,
  {IN}  Npreq,
  {OUT} Nbusrq,
! state machine inputs
  {IN}  Ninit,   ! only for test sync., state machine must 
  {IN}  Nreset,
  {IN}  romdec,
  {IN}  ramdec,
  {IN}  iodec,
  {IN}  progdec,
  {IN}  la[3:2],
  {IN}  Niogt,
  {IN}  eight,
  {IN}  maxseq,
  {IN}  burst,
! inputs
  {IN}  curdrq,
  {IN}  vsnddrq,
  {IN}  snd0drq,
  {IN}  trandrq,
  {IN}  snd1drq,
  {IN}  refdrq,
  {IN}  iodrq,
  {IN}  dmadone,
  {IN}  snd0cod,
! outputs
  {OUT} dmagoing,
  {OUT} dmach[2:0],
  {OUT} Niorq,
  {OUT} defrclk,
  {OUT} romgo,
  {OUT} ramgo,
  {OUT} proggo,
  {OUT} dmarq,
  {OUT} dmavbus, ! vidrq, sndrq0
  {OUT} mclken,
  {OUT} iomclkl
)


! ###############################################################
! MCLK generation

  iodone  = $SGate2(Niorq, Niogt) => Niodone
                   WITH (op=OR, delay=ns_2)
  iomclk  = $SGate2(iogoing, Niodone) => iomclk
                   WITH (op=AND, delay=ns_2)
  iomclkL = $SDTFF(rclk,iomclk,Vdd,Vdd) => (iomclkL,NiomclkL)
               WITH (delay=ns_4, edge=+ve)
  snk1 = SNK(NiomclkL)


! ###############################################################
! 2nd processor bus arbitration
! added before the MCLK(opening) latch that follows
! (critical path timing requirement)
! and note Npreq will have earlier timing than Nmreq

  NpreqL = $SDTFF(mclk,Npreq,Vdd,Vdd) => (NpreqL,preqL)
              WITH (delay=ns_4, edge=-ve)
  N2psel = $SGate2(Npreq, NpreqL) => N2psel
              WITH (op=AND, delay=ns_1)
  brqmux = $SMux(N2psel, Npreq, Nmreq) => iNbusrq
              WITH (delay=ns_2)
  snk2   = SNK(preqL)


! ###############################################################
! busrq generation (clearable latch prefered)

  busrq1 = $NSLatch(mclk, iNbusrq) => busrq1
               WITH (delay=ns_2)
  busrq  = $SGate2(busrq1, Nreset) => busrq
               WITH (op=AND, delay=1)
 Nbusrq  = $SGate1(busrq)          => Nbusrq WITH (delay=ns_1,OP=INV)

! ###############################################################
! BUSSM state machine
!  falling edge of RCLK D-type registered output stage

 bussm = bussm(
     rclk,
     Ninit,
     busrq,
     dmarq,
     ramdec,
     romdec,
     progdec,
     iodec,
     la[3:2],
     Niogt,
     eight,
     maxseq,
     burst
   )
   =>  (
     dmagoing,
     Niorq,
     iogoing,
     armbus,
     defrclk,
     mclken
   )


! ###############################################################

! busrq factored in at last stage for speed
  go = $SGate3(rclk,armbus,Nuldmarq) => go
                   WITH (op=AND, delay=ns_1)

  romgo = $SGate3(romdec,go,rclk) => romgo
                   WITH (op=AND, delay=ns_1)

  ramgo = $SGate3(ramdec,go,rclk) => ramgo
                   WITH (op=AND, delay=ns_1)

  proggo = $SGate3(progdec,go,rclk) => proggo
                   WITH (op=AND, delay=ns_1)


! ###############################################################

  busarb = $BUSARB(
  {IN}  rclk,
  {IN}  Nreset,
  {IN}  dmadone,
  {IN}  dmagoing,
  {IN}  curdrq,
  {IN}  vsnddrq,
  {IN}  snd0drq,
  {IN}  trandrq,
  {IN}  snd1drq,
  {IN}  refdrq,
  {IN}  iodrq, 
  {IN}  snd0cod,
  {OUT} dmarq,
  {OUT} Nuldmarq,
  {OUT} dmach[2:0],
  {OUT} dmavbus,
  {OUT} dmabus
)

WITH (delay=ns_10)

  snkdmabus = SNK(dmabus)

END {BUSCTL}
